module wb_sel_gen(i_ls_part, i_ls_half, i_loaddr, o_wb_sel);

input             i_ls_part;
input             i_ls_half;
input      [ 1:0] i_loaddr;
output reg [ 3:0] o_wb_sel;

always @* begin
  if (i_ls_part) begin
    if (i_ls_half) begin
      case (i_loaddr)
        2'b00: o_wb_sel = 4'b0011;
        2'b01: o_wb_sel = 4'b0110;
        2'b10: o_wb_sel = 4'b1100;
        2'b11: o_wb_sel = 4'b1000;
      endcase
    end else begin
      case (i_loaddr)
        2'b00: o_wb_sel = 4'b0001;
        2'b01: o_wb_sel = 4'b0010;
        2'b10: o_wb_sel = 4'b0100;
        2'b11: o_wb_sel = 4'b1000;
      endcase
    end
  end else begin
    case (i_loaddr)
      2'b00: o_wb_sel = 4'b1111;
      2'b01: o_wb_sel = 4'b1110;
      2'b10: o_wb_sel = 4'b1100;
      2'b11: o_wb_sel = 4'b1000;
    endcase
  end
end

endmodule
